Timing verification of application-specific integrated circuits ebook

Author Evgeni Perelroyzen. Publisher CRC Press. Release 03 October Subjects Computer Technology Technology Nonfiction. Search for a digital library with this title Search by city, ZIP code, or library name Learn more about precise location detection.

View more libraries The first two chapters of the book describe the major tools used for design-for-test. HDL Synthesis. Software Development Systems. Preface This book describes the theory and applications of timing verification of application-specific integrated circuits ASICs.

Timing verification is a relatively new concept, which is why most books on digital systems do not cover the issue. This book lays out the fundamental principles of effective timing verification, and it makes good use of the examples that reflect the current issues facing logic designers. This book is to be used for self-study by practicing engineers. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in design courses in timing analysis and related topics.

The material covered in this book requires some understanding of the Electronic Design Automation EDA tools and an initial course in logic design. Part I chapters 1 and 2 introduces the fundamental concepts involved in timing verification. Including clock definitions, multicycle paths, false paths, and phase-locked loops.

Chapter 1 gives an overview of timing verification and static timing analysis. It contrasts timing verification with functional verification. Typical goals of timing verification in digital systems are presented.

This chapter ends with an example of interface timing analysis. Chapter 2 introduces the concepts of timing analysis with design examples. It specifically discusses such clocking methods as gated clocks, multifrequency clocks, and multiphase clocks. It introduces the concepts of multicycle paths, false paths, and timing constraints such as setup, hold, recovery, and pulse width. Chapter 3 discusses the deep submicron ASIC design flow and application of timing analysis in the design process.

It includes discussion of prelayout and postlayout timing verification. The chapter also discusses behavioral and structural RTL coding for timing, synthesis and timing constraint, and the ASIC sign-off checklist.

We make the concepts concrete with numerous examples. Chapter 4 discusses timing concepts in programmable logic-based designs. It covers design flow, timing parameters, timing analysis, and HDL synthesis and software development systems. We present the most commonly used programmable logic devices Actel, Altera, and Xilinx and associated timing issues. I would like to receive exclusive offers and hear about products from InformIT and its family of brands.

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Pearson automatically collects log data to help ensure the delivery, availability and security of this site. Research in pre-fabrication timing verification and post-fabrication delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts. A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed.

This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit.